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Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge
Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors
Temperature Aware Dynamic Workload Scheduling in Multisocket CPU Servers
An efficient and reliable 1.5-way processor by fusion of space and time redundancies
Runtime Power Management of 3-D Multi-Core Architectures Under Peak Power and Temperature Constraints
