library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all;

entity clock is 
	port (CLKIN : in std_logic; 
	 CLKOUT : out std_logic);
end clock;

architecture A_clock of clock is 
SIGNAL CNT1 : INTEGER RANGE 165000 DOWNTO 0;
SIGNAL M_CLK : std_logic;

BEGIN

PROCESS (CLKIN)
BEGIN
	IF CLKIN'EVENT AND CLKIN = '0' THEN
		IF CNT1 = 164999 THEN
			M_CLK <= NOT M_CLK;
			CNT1 <= 0;
		ELSE
			CNT1 <= CNT1 +1;
		END IF;
		
	END IF;
	
END PROCESS;

CLKOUT <= M_CLK;

end A_clock;
